The block diagram of FIG. 1 of the attached plates of drawings represents a solution (LVDS driver) that has been used for transmitting data signals and clock signals between a driving unit or driver 1 and a receiver 2 using a two-wire line 3, loaded with a resistor 4 at the input of the receiver 2.
In FIG. 1, the reference Vcm designates the “common-mode” voltage source of the two-wire line 3, viewed as differential line, with the voltage source Vcm that is set across the two conductors of the two-wire line 3, through two resistors 6a and 6b, usually assumed to have the same resistance value.
The reference number 7 designates collectively four switches, connected according to a general full-bridge configuration, which enable connection alternatively of one and the other of the conductors of the two-wire line 3 either to a current generator referred to a supply voltage Vcc or to a current generator referred to a ground level G. In the figure, the symbol A designates the logic signal corresponding, respectively, to opening or closing of the individual switches of the bridge 7 (A=switch open, Ā=switch closed), with the value assumed by the symbol A that is able to express the binary value of a datum to be transmitted.
The circuit represented in FIG. 1 is able to cause a current of given intensity to circulate in the load resistor 4, the direction of said current changing as a function of the value of the data bit (“0” or “1”) on the basis of the condition of opening/closing of the switches 7. According to the direction of the current, the voltage across the resistor 4 assumes a positive value (datum=“1”) or negative value (datum=“0”).
In the case where it is desired to transmit both data and a clock signal, i.e., an isochronous pulse train, the diagram of FIG. 1 requires the use of two drivers 1, one for sending the clock signal and the other for sending the data.
FIG. 2 illustrates another diagram, which has been used in MAXIM MAX9223/MAX9224 devices for sending clock signals and data signals on two conductors of a two-wire line (or differential line). Basically, the solution referred to in FIG. 2 envisages transmission of a clock signal that is, to a certain extent, modulated by the logic signal: when the voltage level falls outside the dashed lines, the signal is interpreted as having associated thereto the logic value “1”. When, instead, the signal falls within the interval indicated by the dashed lines, the signal is interpreted as having associated thereto the logic value “0”.